PCIe-SyncClock LP
The PCI-Express SyncClock LP from Brandywine Communications provides precision time with zero latency to the host computer over the PCI bus. An on-board microprocessor automatically
synchronizes the clock to reference signal inputs. The reference signal inputs can be 1 PPS, IRIG or NASA time codes and optionally, GPS or HaveQuick. The clock can free run and be set by commands from the host over the PCI Express bus.
The on-board clock accepts an IRIG A, B, or NASA 36 input and accepts user input reference input signal delay information. An IRIG-B code generator is available.
No matching variations found.
PCIe SyncClock32 with IEEE 1344 In and a Disciplined TCXO Oscillator Option
Model #PCIe-1344UTCIN-TCXO
PCIe SyncClock32 IRIG B Output, OCXO Oscillator Option, and GPS Bracket
Model #PCI-e-BOUT-GT-DOSC-GPSB
PCIe SyncClock32 with Disciplined TCXO Option and IRIG G Input
Model #PCIe-DTCXO-IRIG G IN
Variations
| Model Number | Description | Oscillator Type | Interface Bus | Form Factor | Power Type | Output Format | Input Format |
|---|---|---|---|---|---|---|---|
| PCIe 1344 IN/OUT | PCIe SyncClock32 with IEEE 1344 In and Out | TCXO | PCI Express | Full Height | Bus Power | IEEE 1344 | IEEE 1344, IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCIe Sync+BOUT | PCIe SyncClock32 with IRIG B Output | TCXO | PCI Express | Full Height | Bus Power | IRIG B | IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCIe-1344UTCIN-TCXO | PCIe SyncClock32 with IEEE 1344 In and a Disciplined TCXO Oscillator Option | Disciplined TCXO | PCI Express | Full Height | Bus Power | IEEE 1344 | IEEE 1344, IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCI-e-BOUT-GT-DOSC-GPSB | PCIe SyncClock32 IRIG B Output, OCXO Oscillator Option, and GPS Bracket | OCXO | PCI Express | Full Height | Bus Power | IRIG B | GPS, IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCIe-DCINRS422J3-BOUT | PCIe SyncClock32 with DC RS-422 Input, and IRIG B Output | TCXO | PCI Express | Full Height | Bus Power | IRIG B | RS422, IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCIe-DTCXO-IRIG G IN | PCIe SyncClock32 with Disciplined TCXO Option and IRIG G Input | Disciplined TCXO | PCI Express | Full Height | Bus Power | IRIG B | IRIG A, IRIG B, IRIG G, NASA 36 (1KHz Carrier) |
| PCieLP-SYNC | PCIe SyncClock32, Low Profile Version, ROHS Certified | TCXO | PCI Express | Low Profile | Bus Power | IRIG B | IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCIEX-1PPSINJ2 | PCIe SyncClock32 with 1PPS Input | TCXO | PCI Express | Full Height | Bus Power | IRIG B | 1PPS IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCIEX-SYNCCLOCK32 | PCIe SyncClock32 | TCXO | PCI Express | Full Height | Bus Power | IRIG B | IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCIEX-SYNCCLOCK32-L | PCIe SyncClock32, Low Profile | TCXO | PCI Express | Low Profile | Bus Power | IRIG B | IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
| PCI-EX-SYNCCLOCK32-ROHS | PCIe SyncClock32, ROHS Certified | TCXO | PCI Express | Full Height | Bus Power | IRIG B | IRIG A, IRIG B, NASA 36 (1KHz Carrier) |
Features
- Single-slot low profile 32 bit PCI Express module
- IRIG A, B, NASA 36, 1 PPS sync inputs
- GPS sync option (maintains single-slot)
- HaveQuick sync input option
- Propagation delay correction
- Zero latency time reads
- Match Time output
- IRIG-B time code output (option)
- External Event time tags
- Three user programmable rates
- Supports Windows 8 & 10
- Digitally Signed WHQL Driver
- Designed for Low Profile PCI Express slots.
The advanced microprocessor on the PCI-Express SyncClock LP module constantly measures the time error between the on-board clock and the reference input code and adjusts the error measurement for propagation delay. In units with a disciplined TCXO or OCXO the residual error is used in an adaptive gain loop to adjust the frequency of the oscillator for minimum error. If the incoming time code is missing, or corrupted by noise, the on-board clock is updated using the disciplined oscillator. When the input code is again useable the correction loop is smoothly closed.
58 bits of BCD time data are available to the host computer using two zero latency time reads. The time message contains units of microseconds through units of years. A status word is available using an additional read.
The exact time-of-occurrence of random external events may be captured by using the Event Time input. When the event input is sensed the current time is saved in a buffer for later interrogation by the host. The resolution of the time tag is 100 nanoseconds.
Internal or external processes may be automatically initiated or terminated by using the Match Time feature. This feature asserts an output when the clock’s time matches that of the user input start time. The output is terminated under user control or when the pre-programmed stop time is encountered. The resolution of the Match Time comparison is one microsecond.
Three user programmable pulse rates are provided. Two pulse rates, Clock Low and Clock High, are available on the multi-pin connector. The third rate generator provides heartbeat timing to the host. The divider for each of the three rate generators is programmable by the host over the range 2–65,535. The inputs to the rate generators are 3 MHz or 100 Hz for the heartbeat, 3 MHz for Clock High and 100 Hz for Clock Low.
The GPS synchronization option adds worldwide time transfer capability that can be traced to the U.S. Government standard UTC-USNO. Very precise synchronization, automatic leap year and leap second correction, and accurate position information are additional benefits provided by the GPS option.
Software packages for Windows, VxWorks and Linux are available. C language samples are supplied with the PCI-Express.
In addition to the comprehensive set of standard capabilities of the PCI-Express, Brandywine Communications offers a wide range of options that may be specified. These options allow the user to customize the PCI-Express to fit almost any application.
